Many integrated circuits require transistors capable of switching high voltages that may be 10 volts or more in addition to the core transistor logic that switch at nominal voltages such as 1.0 or 1.5 volts. Adding high voltage transistors to a baseline CMOS process flow often incurs additional process complexity which raises cost.
One solution is to utilize lightly doped drain MOS (LDMOS) transistors. (sometimes referred to as drain extended or DEMOS transistors) which can switch high voltages and can be formed using a baseline CMOS process flow with no additional processing steps. LDMOS transistors may be either n-type (LDNMOS) or p-type (LDPMOS).
As the voltage at which a LDNMOS transistor switches is raised, the acceleration of electrons in the channel is increased resulting in the generation of channel hot carriers (CHC). These hot carriers may have sufficient energy to overcome the substrate/gate dielectric barrier and maybe injected into or through the gate dielectric and also may damage the substrate/gate dielectric interface near the drain end of the LDNMOS channel when the LDNMOS transistor is on. Some of these hot carriers may get trapped in the gate dielectric forming trapped charge. Some of these hot carriers may damage the substrate/gate dielectric interface forming charged interface states. These trapped charges and charged interface states may build up over time causing the turn on voltage of the transistor to increase over time. The increase in turn on voltage and transistor resistance may degrade the transistor performance to the extent that the circuit may fail. In addition, the current of CHC electrons through the gate dielectric degrades the dielectric over time to the point where it may fail causing the integrated circuit to fail.